1. Field
Exemplary embodiments of the present invention relate to a memory and a test method for a memory.
2. Description of the Related Art
As memory devices are highly integrated, a test of memory devices is performed for a long period of time using high-priced test equipment to ensure the reliability of memory chips.
A compression test (or parallel test) that reduces testing time is used as a test for memory devices. Hereafter, the compression test will be described.
In a device test technique, performing a reliable test is important, but a high speed test may be performed for a few thousand of cells. Particularly, since the reduction in test time until products are released as well as a reduction in development time of memory devices has immediate influence on product cost, the reduction in test time serves as a very important issue in efficiency and competition between manufacturers.
In a memory device, when producing a memory chip and performing a test for each cell to decide whether cells of the memory chip pass or fail, the test time of the highly integrated memory device is long, and an increase in cost is caused.
Accordingly, the compression test is used to reduce the test time. In the compression test, the same data is written in a plurality of cells, and a read operation is subsequently performed using an exclusive OR gate or logic gate. If the same data is read in the plurality of cells, a test result is decided as ‘1,’ i.e., pass. If another data is read in at least one of the plurality of cells, the test result is decided as ‘0,’ i.e., memory cell that failed a test. Accordingly, the test time can be reduced.
In the parallel test, a read/write operation of data is performed by simultaneously activating a plurality of cell array regions included in the memory device. The data outputted from the plurality of cell array regions is converted into ‘compressed data’ through a compression process and subsequently outputted to a circuit outside of the memory device. Thus, the pass/fail of the memory device may be checked using the ‘compressed data’ outputted as described above.
In an embodiment where the compression test is performed, the test for the memory device may be quickly performed. However, when the memory device is decided as a memory cell that failed a test, which cell array has the fail among a plurality of cell arrays of the memory device cannot be checked.
An embodiment where data outputted in two or more cell arrays is compressed as ‘1-bit compressed data’ will be described. When the value of the ‘compressed value’ is ‘0,’ the compression test decides that a fail occurs in the two or more cell arrays. However, since the data outputted in the two or more cell arrays is compressed as the ‘1-bit compressed data,’ the compression test cannot check which cell array has the fail from the two or more cell arrays.